Nonvolatile semiconductor memory devices, such as a NAND-type flash memory, structured to have a floating gate as a charge storage layer have increased in application, and are thus requested to perform higher-speed data writing, reading, and erasing. Accordingly, a peripheral transistor circuit in the NAND-type flash memory needs to achieve a high speed. That is, it is necessary reduce a delay time in the peripheral transistor circuit.
The delay time in the peripheral transistor circuit is determined by the parasitic resistance or capacitance of transistors or wiring lines provided in the peripheral transistor circuit. Conventionally, a silicon oxide film or a silicon nitride film is used for a gate sidewall insulating film of the transistor. The relative dielectric constant of the silicon oxide film is about 3.9, and the relative dielectric constant of the silicon nitride film is about 7.0.
The transistors constituting the peripheral transistor circuit respectively have, as parasitic capacitances of the transistors, a capacitance between a gate and a diffusion layer, and a capacitance between a gate and a diffusion layer electrode (contact plug). Since the silicon oxide films or silicon nitride films are disposed between the gate and the diffusion layer and between the gate and the diffusion layer electrode, the parasitic capacitances of the transistors are increased. It is therefore important to reduce these parasitic components to reduce the delay time.